Research Article
Test Access Port and Scan Based Technique of In-System Timing Extraction and Control
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 1 - Issue 17 |
| Published: February 2010 |
| Authors: Richa Maheshwari, Neeta Awasthi |
10.5120/368-555
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Richa Maheshwari, Neeta Awasthi . Test Access Port and Scan Based Technique of In-System Timing Extraction and Control. International Journal of Computer Applications. 1, 17 (February 2010), 21-24. DOI=10.5120/368-555
@article{ 10.5120/368-555,
author = { Richa Maheshwari,Neeta Awasthi },
title = { Test Access Port and Scan Based Technique of In-System Timing Extraction and Control },
journal = { International Journal of Computer Applications },
year = { 2010 },
volume = { 1 },
number = { 17 },
pages = { 21-24 },
doi = { 10.5120/368-555 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2010
%A Richa Maheshwari
%A Neeta Awasthi
%T Test Access Port and Scan Based Technique of In-System Timing Extraction and Control%T
%J International Journal of Computer Applications
%V 1
%N 17
%P 21-24
%R 10.5120/368-555
%I Foundation of Computer Science (FCS), NY, USA
Abstract
Historically, most Printed Circuit Board (PCB) testing was done using bed-of-nail in-circuit test equipment. The progress in the field of miniaturization and integration density has possible to design very complex PCBs, which presents very high testability requirements. Boundary scan is now the most promising technology for testing high complexity PCBs. This paper presents scan-based test access port standard for testing complex ICs and also presents a method which allow the extraction of fine-grained timing information using Test Access Port (TAP).
References
- IEEE Standards Committee. IEEE Standard Test Access Port and Boundary-Scan Architecture. IEEE, 345 East 47th Street, New York, NY 10017-2394, July 1990. IEEE Std 1149.1-1990.
- Andr´e DeHon, Thomas F. Knight Jr., and Thomas Simon. Automatic Impedance Control. In ISSCC Digest of Technical Papers, pages 164-165. IEEE, February 1993.
- Mark Horowitz, Andy Chan, Joe Cobrunson, Jim Gasbarro, Thomas Lee, Wing Leung, Wayne Richardson, Tim Thrush, and Yasuhiro Fujii. PLL Design for a 500MB/s Interface. In ISSCC Digest of Technical Papers, pages 160-161. IEEE, February 1993.
- Mark G. Johnson. A Variable Delay Line PLL for CPU-Coprocessor Synchronization. IEEE Journal of Solid-State Circuits, 23(5):1218-1223, October 1988.
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