Abstract

In this paper we have proposed a look-up-table (LUT) based structure for high-throughput implementation of multilevel lifting DWT. The proposed structure can process one block of samples to achieve high-throughput rate. Compared with the best of the similar existing structure, it does not involves any multipliers but it requires more adders and 21504 extra ROM words for J=3; its offers less critical path delay as compared to exiting structure. Synthesis results show that proposed structure has less ADP 56% less area and 13% less power compared to existing structure for block size J=2. Similarly proposed structure has 64% ADP and less power 21% as compared to existing structure for J=3. The proposed structure is fully scalable for higher block-sizes and it can offer flexibility to derive area-delay efficient structures for various applications.

References

• Y. Meyer, Wavelets: Algorithms and Applications. Philadelphia: Society for Industrial and Applied Mathematics (SIAM), 1993.
• M. Vishwanath, The recursive pyramid algorithm for the discrete wavelet transform, IEEE Trans. Signal Processing, vol. 42, no. 3,pp. 673676, Mar. 1994.
• P.-C. Wu and L.-G. Chen, “An efficient architecture for two-dimensional discrete wavelet transform,” IEEE Trans. Circuits and Systems for Video Technology, vol. 11, no. 4, pp. 536–545, Apr. 2001.
• W. Sweldens, “The lifting scheme: A costom-designe construction of biorthogogal wavelets, ” Applied and Computational Harmonic Analysis, vol. 3, no. 2, pp. 186–200, 1996.
• H. Liao, M. K. Mandal, and B. F. Cockburn, “Efficient architecture for 1-D and 2-D lifting-based wavelet transform,” IEEE Trans. Signal Process., vol. 52, no. 5, pp.1315-1326, May 2004.
• C.-T. Huang, P.-C. Tseng, and L.-G. Chen, “Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform,” IEEE Trans. Signal Processing, vol. 53, no. 4, pp. 1575–1586, Apr. 2005.
• C.-C. Cheng, C.-T. Huang, C.-Y. Cheng, C.-Jr. Lian and L.-G. Chen, “On-chip memory optimization scheme for VLSI implementation of line-based two dimensional discrete wavelet transform,” IEEE Trans. on circuit and System for Video Technology, vol. 17, no. 7, pp. 814-822, July 2007.
• B. K. Mohanty and P. K. Meher, “Memory efficient modular VLSI architecture for high throughput and low-latency implementation of multilevel lifting 2-D DWT,” IEEE Trans. Signal Process., vol. 59, no. 5,pp. 2072–2084, 2011.
• X. Tian, L. Wu, Y.-H.Tan, and J.-W. Tian, “Efficient multi-input/multi-output VLSI architecture for two-dimensional lifting-based discrete wavelet transform,” IEEE Trans. Comput., vol. 60, no. 8, pp.1207–1211, 2011
• B. K. Mohanty, A. Mahajan, and P. K. Meher, “Area- and power-efficient architecture for high-throughput implementation of lifting 2-D DWT,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 59, no. 7, pp.434–438, 2012.
• Y Hu, and C C Jong “A Memory-Efficient High-Throughput Architecture for Lifting-Based Multi-Level 2-D DWT” IEEE Transactions on signal processing, vol. 61, no. 20, October 15 2013.
• B K Mohanty, and A Choubey “Efficient Design for Radix-8 Booth Multiplier and Its Application in Lifting 2-D DWT” Circuits System Signal Processing (CSSP) Vol.36 pp.1129–1149.(2017)