Research Article
Compact CPLD Board Designing and Implemented for Digital Clock
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 3 - Issue 11 |
| Published: July 2010 |
| Authors: Rabinder Henry, Bhushan Patil, Praveen Malav |
10.5120/783-1108
|
Rabinder Henry, Bhushan Patil, Praveen Malav . Compact CPLD Board Designing and Implemented for Digital Clock. International Journal of Computer Applications. 3, 11 (July 2010), 7-10. DOI=10.5120/783-1108
@article{ 10.5120/783-1108,
author = { Rabinder Henry,Bhushan Patil,Praveen Malav },
title = { Compact CPLD Board Designing and Implemented for Digital Clock },
journal = { International Journal of Computer Applications },
year = { 2010 },
volume = { 3 },
number = { 11 },
pages = { 7-10 },
doi = { 10.5120/783-1108 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2010
%A Rabinder Henry
%A Bhushan Patil
%A Praveen Malav
%T Compact CPLD Board Designing and Implemented for Digital Clock%T
%J International Journal of Computer Applications
%V 3
%N 11
%P 7-10
%R 10.5120/783-1108
%I Foundation of Computer Science (FCS), NY, USA
Abstract
The work describes the design and implementation of Complex Programmable Logic Devices (CPLDs) board for many digital applications in the educational and research field laboratory in the university. The objective of designed board is to implement the digital logic, which can be used for any digital application and take advantages of CPLDs features like reconfigurable architecture, high speed operation, pin locking, in-system programming (ISP) for digital system design. This CPLD board size is relatively compact; so it can be easily mounted. On board power supply and variable frequency oscillator improves functionality of overall board. The design includes some cost effective embedded control and communication interface to build digital application to work more efficiently in the market.
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