Research Article
Modified Booth Multiplier with Carry Select Adder using 3-stage Pipelining Technique
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 44 - Issue 14 |
| Published: April 2012 |
| Authors: Kulvir Singh, Dilip Kumar |
10.5120/6334-8710
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Kulvir Singh, Dilip Kumar . Modified Booth Multiplier with Carry Select Adder using 3-stage Pipelining Technique. International Journal of Computer Applications. 44, 14 (April 2012), 35-38. DOI=10.5120/6334-8710
@article{ 10.5120/6334-8710,
author = { Kulvir Singh,Dilip Kumar },
title = { Modified Booth Multiplier with Carry Select Adder using 3-stage Pipelining Technique },
journal = { International Journal of Computer Applications },
year = { 2012 },
volume = { 44 },
number = { 14 },
pages = { 35-38 },
doi = { 10.5120/6334-8710 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2012
%A Kulvir Singh
%A Dilip Kumar
%T Modified Booth Multiplier with Carry Select Adder using 3-stage Pipelining Technique%T
%J International Journal of Computer Applications
%V 44
%N 14
%P 35-38
%R 10.5120/6334-8710
%I Foundation of Computer Science (FCS), NY, USA
Abstract
This paper presents a high-speed and low area 16 ×16 bit Modified Booth Multiplier (MBM) by using Carry Select Adder (CSA) and 3-stage pipelining technique. CSA improves the performance of MBM and pipelining technique reduces the delay time. Using these techniques, the delay is reduced by 56% and the numbers of SLICES and LUT's are reduced by 4% as compared to high speed MBM. The multiplier circuit is designed using VHDL and simulated using Xilinx ISE Simulator. The power metric of the MBM is evaluated using Cadence tools
References
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