Research Article
Speeding-up Phase-Locked Loops based on Adaptive Loop Bandwidth
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 61 - Issue 3 |
| Published: January 2013 |
| Authors: Dina M. El-Laithy, Abdelhalim Zekry, Mohamed Abouelatta |
10.5120/9905-4494
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Dina M. El-Laithy, Abdelhalim Zekry, Mohamed Abouelatta . Speeding-up Phase-Locked Loops based on Adaptive Loop Bandwidth. International Journal of Computer Applications. 61, 3 (January 2013), 1-6. DOI=10.5120/9905-4494
@article{ 10.5120/9905-4494,
author = { Dina M. El-Laithy,Abdelhalim Zekry,Mohamed Abouelatta },
title = { Speeding-up Phase-Locked Loops based on Adaptive Loop Bandwidth },
journal = { International Journal of Computer Applications },
year = { 2013 },
volume = { 61 },
number = { 3 },
pages = { 1-6 },
doi = { 10.5120/9905-4494 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2013
%A Dina M. El-Laithy
%A Abdelhalim Zekry
%A Mohamed Abouelatta
%T Speeding-up Phase-Locked Loops based on Adaptive Loop Bandwidth%T
%J International Journal of Computer Applications
%V 61
%N 3
%P 1-6
%R 10.5120/9905-4494
%I Foundation of Computer Science (FCS), NY, USA
Abstract
This paper describes three techniques for controlling the loop filter of the PLL for high operating speed. The proposed fast-locking PLL reduces the pull-in time and enhances the switching speed, while maintaining better noise bandwidth. Extended loop bandwidth enhancement is achieved by the adaptive control on the loop filter resistances. This work differs from previously published results in that it presents a comprehensive study for modeling, circuit simulation and practical circuit implementation of a 2nd order PLL with loop filter control for speeding-up the PLL. The overall improvement in performance of the proposed PLL is evaluated and compared with the conventional PLL. An industrial CMOS IC is used to implement the PLL.
References
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