Research Article
An Area Efficient design of Fully Pipelined, 2D-DCT, Quantizer and Zigzag JPEG Encoder using VHDL
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 65 - Issue 10 |
| Published: March 2013 |
| Authors: Durga Patidar, Jaikaran Singh, Mukesh Tiwari |
10.5120/10964-5935
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Durga Patidar, Jaikaran Singh, Mukesh Tiwari . An Area Efficient design of Fully Pipelined, 2D-DCT, Quantizer and Zigzag JPEG Encoder using VHDL. International Journal of Computer Applications. 65, 10 (March 2013), 42-46. DOI=10.5120/10964-5935
@article{ 10.5120/10964-5935,
author = { Durga Patidar,Jaikaran Singh,Mukesh Tiwari },
title = { An Area Efficient design of Fully Pipelined, 2D-DCT, Quantizer and Zigzag JPEG Encoder using VHDL },
journal = { International Journal of Computer Applications },
year = { 2013 },
volume = { 65 },
number = { 10 },
pages = { 42-46 },
doi = { 10.5120/10964-5935 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2013
%A Durga Patidar
%A Jaikaran Singh
%A Mukesh Tiwari
%T An Area Efficient design of Fully Pipelined, 2D-DCT, Quantizer and Zigzag JPEG Encoder using VHDL%T
%J International Journal of Computer Applications
%V 65
%N 10
%P 42-46
%R 10.5120/10964-5935
%I Foundation of Computer Science (FCS), NY, USA
Abstract
Image compression is the reduction or elimination of redundancy in data representation in order to achieve reduction in storage and communication cost. For this we use the simple computational method, 2D-DCT, using two 1D-DCT performed on matrix of (8X8). The DCT is a technique that converts a signal from spatial domain to frequency domain. Here we first convert the image into minimum code units. Then 2-D DCT is applied on each block. Then further process of Quantization, Zig-Zag approach and encoding is applied on the processed data. The architecture uses 3049 slices, 2,457 LUT, 46 I/Os of Xilinx Spartan-3 XC3S1600
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