Abstract

Digital sub-threshold circuits are significant for ultra-low power (ULP) applications. Operating circuits at ultra-low voltage levels leads to the less power per operation. An optimized method is separating the logic blocks based on performance requirement and utilizing multiple-supply voltage (VDD) for each blocks. In order to prevent an enormous static current in these multi-VDD circuits, voltage level converters are required. The advantages of single-supply level converter (SSLC) over dual-supply level converter (DSLC) are on the grounds of pin count, congestion in supply routing, complexity and overall system cost. In this paper, a novel sub-threshold single-supply voltage level converter (S_SSLC) based on dynamically-controlled body biasing technique is presented. In this work, a dynamically-controlled body biasing is utilized for setting the threshold voltages of the transistors in order to reduce the delay. This dynamic design can convert an input signal at sub-threshold/super–threshold region ranging from 0. 3v-1. 2v to 1. 2v as output. Simulation results at 180nm CMOS technology node demonstrate the superiority of the proposed design compared to the conventional SSLC designs.

References

• S. N. Wooters, B. H. Calhoun and T. N. Blalock "An Energy-Efficient Subthreshold LevelConverter in 130-nm CMOS," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 4, pp. 290 – 294, Apr. 2010.
• A. Wang, A. Chandrakasan, and S. Kosonocky, "Optimal supply and threshold scaling for subthreshold CMOS circuits," in Proc. IEEE Comput. Soc. Annu. Symp. VLSI, 2002, pp. 5–9.
• I. J. Chang, J. -J. Kim, and K. Roy, "Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2. 5 V," IEEE Trans. Very Large Scale Integr. (VLSI) Syst, vol. 19, no. 8, pp. 1429 – 1437, Aug. 2011.
• H. Soeleman and K. Roy, "Ultra-low power digital subthreshold logic circuits," in Proc. ISPLED, 1999, pp. 94–96.
• A. Wang, B. H. Calhoun, A. P. Chandrakasan, Sub-threshold Design for Ultra Low-Power Systems, 233 Spring Street, New York, NY 10013, USA, 2006.
• K. Navi, M. H. Moaiyeri, R. Faghih Mirzaee, O. Hashemipour, and B. Mazloom Nezhad, "Two new low-power full adders based on majority-not gates," Elsevier, Microelectronics Journal, Vol. 40, No. 1, pp. 126-130, Jan. 2009.
• M. H. Moaiyeri, R. Faghih Mirzaee, K. Navi, T. Nikoubin, and O. Kavehei, "Novel Direct Designs for 3-Input XOR Function for Low Power and High-Speed Applications," Taylor and Francis, International Journal of Electronics, Vol. 97, No. 6, pp. 647-662, Jun. 2010.
• A. Wang and A. Chandrakasan, "A 180-mV subthreshold FFT pro-cessor using a minimum energy design methodology," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 310–319, Jan. 2005.
• H. Soeleman and K. Roy, "Ultra-low power digital subthreshold logic circuits," in Proc. Int. Symp. Low Power Electron. Des. (ISLPED), 1999, pp. 94–96.
• Q. A. Khan, S. K. Wadhwa and K. Misri. , "A Single Supply Level Shifter for Multi-Voltage Systems," 19th Internation Conference on VLSI Design, pp. 557-560, 2006.
• R. Puri, L. Stok, J. Cohn, D. S. Kung, D. Z. Pan, D. Sylvester, A. Srivastava, S. Kulkarni, "Pushing ASIC Performance in a Power Envelope," DAC-40: ACM/IEEE Design Automation Conference, pp. 788-793, Anaheim, CA, June. 2003.
• J. Y. An, H. S. Park and Y. H. Kim, "Level Up/Down Converter with Single Power-Supply Voltage for Multi-VDD Systems," the semiconductor technology and science journal, vol. 10, no. 1, March, 2010.
• A. Chavan, E. M. Donald, Electrical and Computer Engineering Department, University of Texas at El Paso IEEEAC paper 2007.
• J. Kil, J. Gu, and C. Kim, "A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 16, no. 4, pp. 456–465, Apr. 2008.
• S. Narendra, V. De, S. Borkar, D. Antoniadis, and A. Chandrakasan, "Full-chip subthreshold leakage power prediction and reduction techniques for sub-0. 18µm CMOS,"IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 501–510, Mar. 2004.
• Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U. K. : Cambridge Univ. Press, 1998.
• B. Zhai, S. Pant, L. Nazhandali, S. Hanson, J. Olson, A. Reeves, M. Minuth, R. Helfand, T. Austin, D. Sylvester, and D. Blaauw, "Energy-efficient subthreshold processor design," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 17, no. 8, pp. 1127–1137, Aug. 2009.
• J. Kwong, Y. Ramadass, N. Verma, and A. Chandrakasan, "A 65 nm sub-vt microcontroller with integrated SRAM and switched capacitor DC–DC converter," IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 115–126, Jan. 2009.
• S. C. Jocke, J. F. Bolus, S. N. Wooters, A. D. Jurik, A. C. Weaver, T. N. Blalock, and B. H. Calhoun, "A 2. 6- ?w sub-threshold mixed-signal ECG SOC," in Proc. Symp. VLSI Circuits," Jun. 2009, pp. 60–61.