|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 7 - Issue 5 |
| Published: September 2010 |
| Authors: Dhananjay E. Upasani, Sandip B. Shrote, Pallavi S.Deshpande |
10.5120/1162-1467
|
Dhananjay E. Upasani, Sandip B. Shrote, Pallavi S.Deshpande . Article:Standby Leakage Reduction in Nanoscale CMOS VLSI Circuits. International Journal of Computer Applications. 7, 5 (September 2010), 1-4. DOI=10.5120/1162-1467
@article{ 10.5120/1162-1467,
author = { Dhananjay E. Upasani,Sandip B. Shrote,Pallavi S.Deshpande },
title = { Article:Standby Leakage Reduction in Nanoscale CMOS VLSI Circuits },
journal = { International Journal of Computer Applications },
year = { 2010 },
volume = { 7 },
number = { 5 },
pages = { 1-4 },
doi = { 10.5120/1162-1467 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2010
%A Dhananjay E. Upasani
%A Sandip B. Shrote
%A Pallavi S.Deshpande
%T Article:Standby Leakage Reduction in Nanoscale CMOS VLSI Circuits%T
%J International Journal of Computer Applications
%V 7
%N 5
%P 1-4
%R 10.5120/1162-1467
%I Foundation of Computer Science (FCS), NY, USA
Most of the portable systems, such as cellular communication devices, and laptop computers operate from a limited power supply. Devices like cell phones have long idle times and operate in standby mode when not in use. Consequently, the extension of battery-based operation time is a significant design goal which can be made possible by controlling the leakage current flowing through the CMOS gate. This article reviews the off-state leakage mechanisms like weak inversion leakage, gate induced drain leakage and channel punchthrough current. Various circuit level techniques to reduce standby leakage and their design trade-off are discussed. Based on the surveyed techniques, a designer would be able to select the appropriate leakage optimization technique for a standby mode.