Research Article

Characterization of 6T SRAM Cell DRV for ULP Applications

by  Sanjay Kr Singh, D. S. Chauhan, B. K. Kaushik, Vaibhav Dipankar, Navneet Kr. Chaurasia
journal cover
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 72 - Issue 20
Published: June 2013
Authors: Sanjay Kr Singh, D. S. Chauhan, B. K. Kaushik, Vaibhav Dipankar, Navneet Kr. Chaurasia
10.5120/12659-9354
PDF

Sanjay Kr Singh, D. S. Chauhan, B. K. Kaushik, Vaibhav Dipankar, Navneet Kr. Chaurasia . Characterization of 6T SRAM Cell DRV for ULP Applications. International Journal of Computer Applications. 72, 20 (June 2013), 27-33. DOI=10.5120/12659-9354

                        @article{ 10.5120/12659-9354,
                        author  = { Sanjay Kr Singh,D. S. Chauhan,B. K. Kaushik,Vaibhav Dipankar,Navneet Kr. Chaurasia },
                        title   = { Characterization of 6T SRAM Cell DRV for ULP Applications },
                        journal = { International Journal of Computer Applications },
                        year    = { 2013 },
                        volume  = { 72 },
                        number  = { 20 },
                        pages   = { 27-33 },
                        doi     = { 10.5120/12659-9354 },
                        publisher = { Foundation of Computer Science (FCS), NY, USA }
                        }
                        %0 Journal Article
                        %D 2013
                        %A Sanjay Kr Singh
                        %A D. S. Chauhan
                        %A B. K. Kaushik
                        %A Vaibhav Dipankar
                        %A Navneet Kr. Chaurasia
                        %T Characterization of 6T SRAM Cell DRV for ULP Applications%T 
                        %J International Journal of Computer Applications
                        %V 72
                        %N 20
                        %P 27-33
                        %R 10.5120/12659-9354
                        %I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper examines the characteristics of 6T SRAM Cell Data Retention Voltage (DRV). It also presents different DRV minimization techniques for ULP applications. The 6T SRAM cell is designed in 180nm CMOS technology. The cell is simulated to by varying different DRV dependent parameters to understand the effects on it.

References
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  • Animesh Kumar, Huifang Qin, Prakash Ishwar†, Jan Rabaey, and Kannan Ramchandran, Fundamental Data Retention Limits in SRAM Standby – Experimental Results, 9th International Symposium on Quality Electronic Design, 2008
  • A. Kumar, H. Qin, P. Ishwar, J. Rabaey and K. Ramachandran, Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM, IEEE, 2007
  • Sanjay Kr Singh, Sampath Kumar, Arti Noor, D. S. Chauhan & B. K. Kaushik, Deep Sub-Micron SRAM design for DRV analysis and low leakage, International Journal of Advances in Engineering & Technology, 2011.
  • Sampath Kumar, Sanjay Kr Singh, Arti Noor and B. K. Kaushik, Deep Sub-Micron SRAM Design for Low Leakage, Int'l Conf. on Computer & Communication Technology, 2010
Index Terms
Computer Science
Information Sciences
No index terms available.
Keywords

CMOS SNM DRV CR PR

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