Research Article
Design of Efficient 16-Bit Parallel Prefix Ladner-Fischer Adder
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 79 - Issue 16 |
| Published: October 2013 |
| Authors: S. Baba Fariddin, E. Vargil Vijay |
10.5120/13943-1784
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S. Baba Fariddin, E. Vargil Vijay . Design of Efficient 16-Bit Parallel Prefix Ladner-Fischer Adder. International Journal of Computer Applications. 79, 16 (October 2013), 10-14. DOI=10.5120/13943-1784
@article{ 10.5120/13943-1784,
author = { S. Baba Fariddin,E. Vargil Vijay },
title = { Design of Efficient 16-Bit Parallel Prefix Ladner-Fischer Adder },
journal = { International Journal of Computer Applications },
year = { 2013 },
volume = { 79 },
number = { 16 },
pages = { 10-14 },
doi = { 10.5120/13943-1784 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2013
%A S. Baba Fariddin
%A E. Vargil Vijay
%T Design of Efficient 16-Bit Parallel Prefix Ladner-Fischer Adder%T
%J International Journal of Computer Applications
%V 79
%N 16
%P 10-14
%R 10.5120/13943-1784
%I Foundation of Computer Science (FCS), NY, USA
Abstract
A parallel-prefix adder gives the best performance in VLSI design. However, performance of Ladner-Fischer adder through black cell takes huge memory. So, gray cell can be replaced instead of black cell which gives the Efficiency in Ladner-Fischer Adder. The proposed system consists of three stages of operations they are pre-processing stage, carry generation stage, post-processing stage. The pre-processing stage focuses on propagate and generate, carry generation stage focuses on carry generation and post-processing stage focuses on final result. In ripple carry adder each bit of addition operation is waited for the previous bit addition operation. In efficient Ladner - Fischer adder, addition operation does not wait for previous bit addition operation and modification is done at gate level to improve the speed and to decreases the memory used.
References
- Pakkiraiah. Chakali, madhu Kumar. Patnala "Design of high speed Ladner - Fischer based carry select adder" IJSCE march 2013
- Haridimos T. Vergos, Member, IEEE and Giorgos Dimitrakopoulos, Member, IEEE," On modulo 2n+1 adder design" IEEE Trans on computers, vol. 61, no. 2, Feb 2012
- David h, k hoe, Chris Martinez and Sri Jyothsna vundavalli "Design and characterization of parallel prefix adders using FPGAs", Pages. 168-172, march2011 IEEE.
- K. Vitoroulis and A. J. Al-Khalili, "performance of parallel prefix adders implemented with FPGA technology," IEEE Northeast Workshop on circuits and systems, pp. 498-501, Aug 2007.
- Giorgos Dimitrakopoulos and Dimitris Nikolos, "High Speed Parallel Prefix . . . Ling adders," IEEE Transactions on Computers, vol. 54, no. 2, February 2005
- S. Knowles," A family of adders,"proc. 15thsymp. Comp. Arith, pp. 277-281, June 2001.
- R. Brent and H. Kung, "A regular layout for parallel adders," IEEE Trans. Computers, vol. C-31, no. 3, pp. 260-264, March 1982.
- R. E. Ladner and M. J. Fischer, "Parallel Prefix Computation," J. ACM, vol. 27, no. 4, pages 831-838, Oct. 1980.
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