Research Article
Fair Chance Round Robin Arbiter
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 81 - Issue 14 |
| Published: November 2013 |
| Authors: Prateek Karanpuria |
10.5120/14187-2446
|
Prateek Karanpuria . Fair Chance Round Robin Arbiter. International Journal of Computer Applications. 81, 14 (November 2013), 36-40. DOI=10.5120/14187-2446
@article{ 10.5120/14187-2446,
author = { Prateek Karanpuria },
title = { Fair Chance Round Robin Arbiter },
journal = { International Journal of Computer Applications },
year = { 2013 },
volume = { 81 },
number = { 14 },
pages = { 36-40 },
doi = { 10.5120/14187-2446 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2013
%A Prateek Karanpuria
%T Fair Chance Round Robin Arbiter%T
%J International Journal of Computer Applications
%V 81
%N 14
%P 36-40
%R 10.5120/14187-2446
%I Foundation of Computer Science (FCS), NY, USA
Abstract
With the advancement of Network-on-chip (NoC), fast and fair arbiter as the basic building block for high speed switches/routers gained attention in recent years. In this paper I propose the fair chance round robin arbiter (FCRRA), a high speed, low power and area efficient RRA for NoC applications. The FCRRAG tool propose in this paper can generate a design for bus arbiter, which can handle the exact number of bus masters for both on chip and off chip buses within one short cycle.
References
- Si Quing Zheng and Mei Yang, "Algorithm Hardware Code sign of Fast Parallel Round Robin Arbiters," IEEE transactions on Parallel and distributed Systems, vol 18, no. 1 January 2007.
- Yihan Li, Shivendra S. Panwar, H. Jonathan Chao, "The Dual Round Robin Matching Switch with Exhaustive Service. "
- M. J. Karol, M. Hluchyj, and S. Morgan, "Input versus output queuing on a space-division packet switch," IEEE Trans. on Communications, vol. 35, pp. 1347-1356, 1987.
- Eung S Chin,Vincent J. Mooney III and George F Riley, "Round Robin Arbiter Design and Generation," ISSS'02, October 2-4 2002 Kyoto, Japan.
- H. J. Chao, C. H. Lam, and X. Guo, "A Fast Arbitration Scheme for Terabit Packet Switches," Proceedings of IEEE Global Telecommunications Conference, 1999, pp. 1236-1243.
- N. Sertac Artan, Ming Yang and H. Jonathan Chao, "Hierarchical Round Robin Arbiter for High Speed, Low-Power and Scalable Networks –on-Chip.
- N. Mckeown, P. Varaiya, and J. Warland, "The iSLIP Scheduling Algorithm for Input-Queued Switch," IEEE Transaction on Networks, 1999, pp. 188-201.
- Nick McKeown,"The iSLIP Scheduling Algorithm for Input-Queued Switches" IEEE/ACM transactions on networking, vol. 7, no. 2, April 1999.
- H. J. Chao and J. S. Park, "Centralized Contention Resolution Schemes for a Larger-capacity Optical ATM Switch," Proceedings of IEEE ATM Workshop, 1998, pp. 11-16.
- P. Gupta and N. Mckeown, "Designing and Implementing a Fast Crossbar Scheduler," IEEE Micro, 1999, pp. 20-28.
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