Research Article
Comments on ìArea ñ Time Efficient Sign Detection Technique for Binary Signed-Digit Number Systemî proposed by Srikanthan, Lam and Suman
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 88 - Issue 15 |
| Published: February 2014 |
| Authors: M. S. Chakraborty, S. K. Sao |
10.5120/15430-4001
|
M. S. Chakraborty, S. K. Sao . Comments on ìArea ñ Time Efficient Sign Detection Technique for Binary Signed-Digit Number Systemî proposed by Srikanthan, Lam and Suman. International Journal of Computer Applications. 88, 15 (February 2014), 38-40. DOI=10.5120/15430-4001
@article{ 10.5120/15430-4001,
author = { M. S. Chakraborty,S. K. Sao },
title = { Comments on ìArea ñ Time Efficient Sign Detection Technique for Binary Signed-Digit Number Systemî proposed by Srikanthan, Lam and Suman },
journal = { International Journal of Computer Applications },
year = { 2014 },
volume = { 88 },
number = { 15 },
pages = { 38-40 },
doi = { 10.5120/15430-4001 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2014
%A M. S. Chakraborty
%A S. K. Sao
%T Comments on ìArea ñ Time Efficient Sign Detection Technique for Binary Signed-Digit Number Systemî proposed by Srikanthan, Lam and Suman%T
%J International Journal of Computer Applications
%V 88
%N 15
%P 38-40
%R 10.5120/15430-4001
%I Foundation of Computer Science (FCS), NY, USA
Abstract
It is shown that the sign detection technique for binary signed-digit number system reported by Srikanthan, Lam and Suman [1] cannot work correctly. The root cause of the problem is detected and some modifications are proposed. The proposed modifications are found to be significant.
References
- Srikanthan, T. , Lam, S. K. and Suman, M. "Area–Time Efficient Sign Detection Technique for Binary Signed–digit Number System," IEEE Trans. Computers, vol. 53, no. 1, pp. 69-72, Jan. 2004.
- Avizienis, A. , "Signed - digit number representation for fast parallel arithmetic", IRE Transactions on Electronic Computers, vol. EC - 10, no. 3, pp. 389 – 400, Sept 1961.
- Parhami, B. , Computer Arithmetic: Algorithms and Hardware Design, 1st ed. , Oxford Univ. Press, USA, Oct 2009.
- Sutherland, I. , Sproull ,R. and Harris, D. , Logical Effort: Designing Fast CMOS Circuits, 1st ed CA, USA: Morgan Kaufmann, Feb. 1999.
- Dao, H. Q. and Oklobdzija, V. G. , "Application of Logical Effort on Delay Analysis of 64-Bit Static Carry-Lookahead Adder",35th Annual Asilomar Conference on Signals, Systems and Computers Pacific Grove, California, Nov. 4-7, 2001.
- He, Y. and Chang, C. – H. , "A Power - Delay Efficient Hybrid Carry - Lookahead/ Carry - Select Based Redundant Binary to Two's Complement Converter", IEEE Transactions on Circuits and Systems - I, vol. 55, no. 1, pp. 336 – 346, Feb. 2008.
- Gorgin, S. and Jaberipur G. , "A Family of High Radix Signed Digit Adders", in 20th IEEE Symposium on Computer Arithmetic, Tubingen, Iran, July 2011.
- Naderpor, F. , and Ko, S. , "Improved Design of High - Radix Signed - Digit Adders," in International Symposium on Electronic System Design, Kolkata, India Dec. 2012.
- Wei S. , "Residue-binary number conversion using signed-digit arithmetic for a four-moduli set", in Proceedings of IEEE Region 10 Conference (TENCON) 2012, Cebu, Philippines, pp. 1-4, Nov 2012.
Index Terms
Keywords