Research Article
Launch and Capture Power Reduction using Data Encoding and Precomputation Technique
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 112 - Issue 11 |
| Published: February 2015 |
| Authors: R.Deepika, V.Sinduja |
10.5120/19713-1483
|
R.Deepika, V.Sinduja . Launch and Capture Power Reduction using Data Encoding and Precomputation Technique. International Journal of Computer Applications. 112, 11 (February 2015), 28-31. DOI=10.5120/19713-1483
@article{ 10.5120/19713-1483,
author = { R.Deepika,V.Sinduja },
title = { Launch and Capture Power Reduction using Data Encoding and Precomputation Technique },
journal = { International Journal of Computer Applications },
year = { 2015 },
volume = { 112 },
number = { 11 },
pages = { 28-31 },
doi = { 10.5120/19713-1483 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2015
%A R.Deepika
%A V.Sinduja
%T Launch and Capture Power Reduction using Data Encoding and Precomputation Technique%T
%J International Journal of Computer Applications
%V 112
%N 11
%P 28-31
%R 10.5120/19713-1483
%I Foundation of Computer Science (FCS), NY, USA
Abstract
Testing of VLSI circuits aims for high quality screening of circuits by targeting performance related faults. The main objective of testing is to generate compact test set which is used to detect multiple faults present in the circuit, which results in increase of switching activity hence the pattern should be optimized without losses in performance of the circuit. Design for Testability mechanism is used for launch-off shift and launch-off capture testing and it supports design partitioning approach in which one region is tested at a time results in launch and capture power reduction in a design flow compatible manner. Data encoding scheme is used to reduce the power dissipation by the means of reducing the switching activity which involves comparison of two bits at a time. By using precomputation technique which involves comparison of single bit at a time starting from its MSB to LSB, the power dissipation is reduced up to 20% compared to data encoding technique.
References
- Samah Mohamed Saeed and Ozgur Sinanoglu "Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing'' IEEE trans. very large scale integration (VLSI) systems, vol. 22, no. 3, march 2014.
- P. Girard, "Survey of low-power testing of VLSI circuits," IEEE Design Test, vol. 19, no. 3, pp. 82–92, May 2009
- M. Palesi, R. Tornero, J. M. Orduñna, V. Catania, and D. Panno,"Designing robust routing algorithms and mapping cores in networks-onchip:A multi-objective evolutionary-based approach," J. Univ. Comput. Sci. , vol. 18, no. 7, pp. 937–969, 2012.
- S. M. Saeed and O. Sinanoglu, "DfT support for launch and capture power reduction in launch-off-capture testing," in Proc. 17th IEEE Eur. Test Symp. pp. 1–6, May 2012.
- J. Savir and S. Patil, "On broad-side delay test," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 2, no. 3, pp. 368–372, Sep. 2013.
- J. Savir and S. Patil, "Scan-based transition test," IEEE Trans. Comput. Aided Design Integr. Circuits Syst. , vol. 12, no. 8, pp. 1232–1241, Aug. 2011.
- O. Sinanoglu, "Rewind-support for peak capture power reduction in launch-off-shift testing," in Proc. 20th Asian Test Symp. , pp. 78–83, Nov. 2011.
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, W. James, D. Finan, A. P. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, , "An 80-tile Sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-StateCircuits, vol. 43, no. 1, pp. 29–41, Jan. 2008.
- S. Youngsoo, C. Soo-Ik, and C. Kiyoung, "Partial bus-invert coding for power optimization of application-specific systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 9, no. 2, pp. 377–383, Apr. 2001.
- Z. Yan, J. Lach, K. Skadron, and M. R. Stan, "Odd/even bus invert with two-phase transfer for buses with coupling," in Proc. Int. Symp. Low Power Electron. Design, 2002, pp. 80–83
Index Terms
Keywords