Research Article
Low Power Adder based ANN
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 118 - Issue 10 |
| Published: May 2015 |
| Authors: S N Prasad, S.Y. Kulkarni |
10.5120/20778-3335
|
S N Prasad, S.Y. Kulkarni . Low Power Adder based ANN. International Journal of Computer Applications. 118, 10 (May 2015), 1-4. DOI=10.5120/20778-3335
@article{ 10.5120/20778-3335,
author = { S N Prasad,S.Y. Kulkarni },
title = { Low Power Adder based ANN },
journal = { International Journal of Computer Applications },
year = { 2015 },
volume = { 118 },
number = { 10 },
pages = { 1-4 },
doi = { 10.5120/20778-3335 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2015
%A S N Prasad
%A S.Y. Kulkarni
%T Low Power Adder based ANN%T
%J International Journal of Computer Applications
%V 118
%N 10
%P 1-4
%R 10.5120/20778-3335
%I Foundation of Computer Science (FCS), NY, USA
Abstract
This paper presents an overview of datapath realizations of the Hardware neural network models which perform massive parallel operations for best results and real time applications. Digital implemented neural models processing element – adder with low power consumption is proposed for real-time multimedia applications. Proposed adder is illustrated in the 2-3-1 tree layer artificial neural network (ANN). Designs were modeled with Verilog HDL and implemented in FPGA domain by targeting the Virtex 7 device.
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