Abstract

The increasing volume of data processing has created a growing gap between memory access and computational speed in conventional computing systems. In a conventional von Neumann architecture, operands are repeatedly transferred between memory and processing units, resulting in additional latency and energy consumption. Inmemory computing (IMC) addresses this limitation by performing selected computations within the memory array itself. SRAM is a promising technology for IMC because of its high operating speed, CMOS compatibility, and suitability for dense memory arrays. In particular, 8T SRAM provides an isolated read path that can be exploited for logic computation without directly disturbing the stored data, while 8+T SRAM provides enhanced read capability for more complex operations. Previous research has demonstrated SRAM-based Boolean functions, Half Adders, and Full Adders using computational read paths. However, achieving an appropriate balance between propagation delay, power consumption, transistor count, sensing complexity, and reliable arithmetic operation remains challenging. This work investigates an in-memory Half Adder and Full Adder architecture based on 8T and 8+T SRAM cells. The 8T SRAM structure is employed for Half Adder computation, while the 8+T SRAM structure is used for Full Adder computation. The proposed circuits are intended for transistor-level implementation and simulation in Cadence Virtuoso, followed by evaluation using propagation delay, power consumption, power-delay product (PDP), transistor count, and functional reliability.

References

• R. S. Siddanath, S. Mondal, M. Goswami, and K. Kandpal, “A Comprehensive Survey of Custom Layout Techniques for 6T, 8T, and 10T SRAM Bitcells Across Planar CMOS and FinFET Technology Nodes,” IEEE Access, 2026, doi: 10.1109/ACCESS.2026.3664102.
• K. Becker, M. Zimmerling, W.-J. Fang, M. L. Fuad, D. K., and H.-G. Herrmann et al., “A 6TSRAM-Based In-Memory Computing System for Sensor-Driven Edge Intelligence,” AI Sensors, 2026.
• K. Desai, Y. Agrawal, S. Rajendran, and V. Palaparthy, “Design and optimization of inmemory half-adder and full-adder circuits using 8T and 8+T SRAM cells for enhanced logic operations,” Microsystem Technologies, vol. 31, pp. 3835–3846, 2025.
• S. S. Kumar and J. Nayak, “Effective 8T Reconfigurable SRAM for Data Integrity and Versatile In-Memory Computing-Based AI Acceleration,” Electronics, vol. 14, no. 13, p. 2719, 2025.
• H.-J. Shin and S.-H. Jo, “Low-Power 8T SRAM Compute-in-Memory Macro for Edge AI Processors,” Applied Sciences, vol. 14, p. 10924, 2024.
• K. Lee, J. Kim, and J. Park, “A 28-nm 50.1TOPS/W P-8T SRAM Compute-In-Memory Macro Design with BL Charge-Sharing-Based InSRAM DAC/ADC Operations,” IEEE Journal of Solid-State Circuits, vol. 59, pp. 1926–1937, 2024.
• L. Wu, C. Wang, and H. Mo, “Optimization of 8T SRAM BIT-cell design,” in Proc. CSTIC, Shanghai, China, 2024.
• P. Tiwari and P. K. Misra, “Fast and energy efficient logic in memory module using SRAM cells,” in Proc. IEEE CONECCT, 2024.
• H. Xiao, R. Zhao, Y. Liu, Y. Liu, and J. Chen, “Bi-Directional and Operand-Controllable InMemory Computing for Boolean Logic and Search Operations with Row and Column Directional SRAM,” Micromachines, vol. 15, 2024.
• T.-D. Nguyen, M.-S. Le, T.-N. Pham, and I.-J. Chang, “TA-Quatro: Soft Error-Resilient and Power-Efficient SRAM Cell for ADC-Less Binary Weight and Ternary Activation In-Memory Computing,” Electronics, vol. 13, 2024.
• L. Chen, C. Shi, J. He, J. Yu, H. Wang, J. Lu, L. Liu, N. Wu, and M. Tian, “An 8-T Processingin-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 11, pp. 4249–4260, 2023.
• S. S. Kumar and J. Nayak, “Efficient implementation of fast half adder using 8T SRAM for in-memory computing applications,” in Proc. MoSICom, 2023.
• K. Soundrapandiyan, S. K. Vishvakarma, and B. S. Reniwal, “Enabling Energy-Efficient InMemory Computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array,” IEEE Journal of Emerging and Selected Topics in Circuits and Systems, vol. 13, pp. 445–455, 2023.
• Z. Xuan, C. Liu, Y. Zhang, Y. Li, and Y. Kang, “A Brain-Inspired ADC-Free SRAM-Based InMemory Computing Macro with High-Precision MAC for AI Application,” IEEE Transactions on Circuits and Systems II, vol. 70, pp. 1276–1280, 2023.
• A. K. Rajput, A. K. Tiwari, and M. Pattanaik, “An energy-efficient hybrid SRAM-based inmemory computing macro for artificial intelligence edge devices,” Circuits, Systems, and Signal Processing, vol. 42, 2023.
• H. Kim, “A 1–16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks,” IEEE Transactions on Circuits and Systems I, vol. 70, 2023.
• S. Song and Y. Kim, “Novel In-Memory Computing Adder Using 8+T SRAM,” Electronics, vol. 11, no. 6, p. 929, 2022.
• J. Jung and Y. Kim, “A High-Performance, Low-Power 8-Bit Full-Adder Using 8+T Differential SRAM for Computation-in-Memory,” in Proc. IEEE ISOCC, pp. 131–132, 2022.
• J. Chen, W. Zhao, Y. Wang, Y. Shu, W. Jiang, and Y. Ha, “A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations,” IEEE Transactions on Very Large Scale Integration Systems, vol. 30, no. 6, pp. 769–780, 2022.
• F. Dong, X. Si, and M.-F. Chang, “Design Methodology and Trends of SRAM-Based Compute-in-Memory Circuits,” in Proc. IEEE ICSICT, 2022.
• S. Kim, W. Lee, S. Kim, S. Park, and D. Jeon, “An In-Memory Computing SRAM Macro for Memory-Augmented Neural Network,” IEEE Transactions on Circuits and Systems II, vol. 69, 2022.
• P. K. Bharti, S. Jain, K. R. Pillai, S. V. Sayyaparaju, G. S. Kalsi, J. Mekie, and S. Subramoney, “Compute-In-Memory Using 6T SRAM for a Wide Variety of Workloads,” in Proc. IEEE ISCAS, 2022.
• Z. Lin, Z. Tong, J. Zhang, F. Wang, T. Xu, Y. Zhao, X. Wu, C. Peng, W. Lu, Q. Zhao, and J. Chen, “A Review on SRAM-Based Computing InMemory: Circuits, Functions, and Applications,” Journal of Semiconductors, vol. 43, no. 3, 2022.
• J. Han and Y. Kim, “A Fast Half Adder Using 8T SRAM for Computation-in-Memory,” in Proc. IEEE ICCE-Asia, 2021.
• C. Yeswanth and A. Acharya, “In-memory Computing Based Boolean and Logical Circuit Design using 8T SRAM,” in Proc. DevIC, pp. 430434, 2021.
• A. K. Gupta and A. Acharya, “Exploration of 9T SRAM Cell for In Memory Computing Application,” in Proc. DevIC, pp. 461–465, 2021.
• J. Zhang, Z. Lin, X. Wu, C. Peng, W. Lu, Q. Zhao, and J. Chen, “An 8T SRAM Array with Configurable Word Lines for In-Memory Computing Operation,” Electronics, vol. 10, no. 3, p. 300, 2021.
• K. Lee, S. Cheon, J. Jo, W. Choi, and J. Park, “A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration,” in Proc. ACM/IEEE DAC, pp. 739–744, 2021.
• M. E. Sinangil et al., “A 7-nm Compute-inMemory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS,” IEEE Journal of Solid-State Circuits, vol. 56, no. 1, pp. 188–198, 2021.
• S. Jain, L. Lin, and M. Alioto, “±CIM SRAM for Signed In-Memory Broad-Purpose Computing from DSP to Neural Processing,” IEEE Journal of Solid-State Circuits, vol. 56, no. 10, pp. 2981– 2992, 2021